Memory drivers, system controllers and transceivers may use an interface signal standard for digital integrated circuits, such as High Speed Transistor Logic (HSTL) (also called High Speed Transceiver Logic) or Stub-Series Transceiver Logic (SSTL)(also called Stub-Series Terminated Logic). The HSTL standard may use input/output (I/O) structures, such as differential amplifier inputs with one input internally tied to a usersupplied input reference voltage, and outputs with output power supply inputs (VCCO/VDDQ).
With HSTL, a high logic output (“1” or VOH) may be represented by a voltage of about 0.95-1.5V volts. A low logic output (“0” or VOL) may represented by a voltage of about 0.55 volts or even lower. The rise and fall times for transitions between logical levels can be as low as 200 to 300 picoseconds (ps).
The application relates to a method and circuit for supplying valid logic values for sampling on high speed interfaces during a reset.
The circuit may use a Thevenin termination methodology to supply a required termination resistor during “normal” operation, while still supplying valid low or high logic values for sampling during “reset.”
The circuit may supply logic values to a microchip that samples during reset on the 10 Gigabit Media Independent Interface (XGMII) operating in HSTL, for example.
An aspect of the application relates to an apparatus comprising first and second termination impedances coupled to a first end of a transmission line and a driver circuit coupled to the first impedance. The driver circuit is configured to supply a first pre-determined voltage level to the first impedance during a normal mode and supply a second pre-determined voltage level to the first impedance during a reset mode. The pre-determined voltage levels cause a logic value to be available for sampling during reset on a second end of the transmission line.
Another aspect relates to a method of supplying termination voltages to a transmission line. The method comprises supplying a first pre-determined voltage level to a first impedance coupled to a first end of a transmission line during a normal mode; and supplying a second pre-determined voltage level to the first impedance during a reset mode. The pre-determined voltage levels cause a logic value to be present for sampling during reset on a second end of the transmission line.
The methods and circuits described herein may be used with memory drivers, transceivers, system controllers, packet processors and other devices.